Overviews

Commands

See Also

Once you have compiled a design in the Quartus^® II software, you can generate output netlist and other output files without recompilation of the design, by using the EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu).

You can use this command to generate Verilog Output Files (.vo), VHDL Output Files (.vho), Standard Delay Format Output Files (.sdo) output netlist files, as well as Stamp model files, PartMiner XML-Format Files (.xml), and IBIS Output Files (.ibs).

To generate an output netlist or other output file:

1. If you have not already done so, open an existing project.

2. If you have not already done so, compile the project.

3. Specify a simulation, timing analysis, or board-level simulation tool.

4. Choose EDA Tool Post-Compilation Commands > Write Output Netlists Command (Processing menu).

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