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The Quartus^® II Simulator is a powerful tool for testing and debugging the logical operation and internal timing of the design entities in your project. Because the Simulator allows you to verify your project before it is actually committed to hardware, it can dramatically shorten the time it takes to transform your initial design concept into working silicon. You can simulate portions of your project (called design entities), or you can simulate an entire Quartus II project, regardless of the number of devices required to implement it.

The Quartus II Simulator can perform two types of simulation: functional simulation and timing simulation. You can specify the type of simulation you wish to perform when you specify Simulator settings.

By performing a functional simulation, you can test the logical operation of your design entity or entire project without the need for timing information. In a functional simulation, the output logic levels change at the same time as the input vectors and no propagation delays are used during simulation.

In contrast, when performing a timing simulation the Simulator uses a compilation netlist that contains all the information for a fully synthesized design entity, that is, it includes only nodes that have "survived" logic synthesis.

In each type of simulation, you can specify a vector source file as the source of simulation input vectors. You can create a Vector Waveform File (.vwf) with the Quartus II Waveform Editor for this purpose, or you can use another supported vector source file format.  More Details

During simulation, the input waveforms in the VWF remain unchanged. The output and buried logic levels in the file are either updated or preserved, according to your specifications. With the Waveform Editor, you can check simulation outputs against any outputs in the VWF. The outputs in the VWF can be expected outputs, outputs from a previous simulation, or actual device outputs.

By specifying Simulator settings, you can also monitor how your design entity responds to glitches and setup and hold time violations.

You can view the output VWF in the Report window when you stop the Simulator manually, or when it reaches a breakpoint or the simulation end time.

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