See Also

A Verilog HDL file (.vo) and a Standard Delay Format Output File (.sdo) are created after you specify VHDL output settings and compile the project.

The Compiler places the generated Verilog Output File into a tool specific directory within the current project directory. For EDA simulation tools, the Verilog Output File is placed in <project directory>/simulation/<EDA simulation tool>. For EDA timing analysis tools, the Verilog Output File is placed in /<project directory>/timing/<EDA timing analysis tool>. If the Custom Verilog HDL or Custom VHDL option is specified in the EDA Tool Settings page of the Settings dialog box (Assignments menu) for simulation or timing analysis, the Verilog Output File is placed in <project directory>/simulation/custom or <project directory>/timing/custom.