EDA Interfaces

Map Illegal Verilog HDL Characters



Maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus® II hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output Files (.vo) . Turning on this option also maps other illegal non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to underscore (_).

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