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To perform a timing simulation of a Verilog or VHDL design with the Model Technology^™ ModelSim^® PE or SE (non-OEM) software:

1. If you have not already done so, perform 4. Map to Libraries and Compile Design Files with the ModelSim Software.

2. If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.

3. Choose Simulate (Simulate menu). The Simulate dialog box appears.

4. If you a simulating a Verilog design, click the Verilog tab. Under Pulse Options, type 0 in the Error Limit and Rejection Limit boxes.

5. If you are simulating a VHDL design, to specify the Standard Delay Format Output File (.sdo):

   1. Click the SDF tab.

   2. Click Add.

   3. In the Add SDF Entry dialog box, click Browse. The Select SDF File dialog box appears.

   4. In the Files of type list, select All Files (*.*).

   5. Select the SDF File.

   6. Click Open.

   7. Click OK.

   If you are using a test bench file to provide simulation stimuli to your design, in the Apply to region box, specify the path to the design instance in the test bench, starting from the top-level design file.

6. Click the Design tab.

7. In the Name list, click the + icon to expand the work directory and select the design entity that corresponds to the SDF Output File.

8. Click Add.

9. Select the top-level Verilog or VHDL Output File or test bench.

10. Click Add.

11. Click Load.

12. Perform the timing simulation in the ModelSim software.

If you are simulating an ARM®-based Excalibur™ design, the bus functional model generates the output.dat bus functional model simulation file. Refer to ModelSim software documentation for more information on how to view and interpret the results of the simulation.

13. To continue with the ModelSim simulation flow, proceed to 6. Locate Signals to Source with the ModelSim Software.

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