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To compile the atom simulation model libraries, Verilog Output File (.vo) or VHDL Output File (.vho), and test bench files in the Model Technology^™ ModelSim^® PE or SE (non-OEM) software:

1. If your design contains the altgxb megafunction, to map to the precompiled Stratix^™ GX timing simulation model libraries:

   1. Choose New > Library (File menu). The Create a New Library dialog box appears.

   2. Under Create, select a new library and a logical mapping to it.

   3. In the Library Name box, type stratixgx_gxb.

   4. In the Library Maps to box, specify the \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\stratixgx_gxb\ directory.

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

2. Choose Compile (Compile menu).

3. In the Library list of the Compile HDL Source Files dialog box, select the work library.

4. In the Files of Type list, select All Files (*.*), and in the Look in list, select the appropriate simulation model library.

   For VHDL 93-compliant designs, turn on Use 1993 Language Syntax under Default Options.

5. Click Compile.

6. If you are performing a timing simulation of an ARM^®-based Excalibur^™ design, repeat steps 2 to 4 to compile the appropriate ARM-based Excalibur simulation model and wrapper files.

7. Repeat steps 2 to 4 for the Verilog or VHDL Output File and the test bench file (if you are using one) that instantiates the Verilog or VHDL Output File.

8. Click Done.

9. To continue with the ModelSim simulation flow, proceed to one of the following steps:

   • 5. Perform a Timing Simulation with the ModelSim Software
   • 5. Perform a Timing Simulation with the ModelSim Software (Command-Line)

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