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To perform a timing simulation of a Verilog or VHDL design with the Model Technology^™ ModelSim^® (OEM) software using command-line commands: Read This First

1. If you have not already done so, perform 4. Compile Libraries and Design Files with the ModelSim Software (Command-Line).

2. If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.

3. To load the design with minimum, typical, or maximum timing values, type the following commands at the ModelSim prompt:

   vsim -sdf(min | typ | max) /=<design name>.sdo work.<top-level design entity> 

4. Perform the timing simulation in the ModelSim software.

If you are simulating an ARM®-based Excalibur™ design, the bus functional model generates the output.dat bus functional model simulation file. Refer to ModelSim software documentation for more information on how to view and interpret the results of the simulation.

5. To continue with the ModelSim simulation flow, proceed to 6. Locate Signals to Source with the ModelSim Software.

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