Overviews

Commands

See Also

To map to the ModelSim^® precompiled libraries (for VHDL designs) and compile the Verilog Output Files (.vo) or VHDL Output File (.vho) and test bench files in the Model Technology^™ ModelSim-Altera^® (OEM) software using command-line commands:

1. If you have not already done so, perform 2. Set Up a Project with the ModelSim-Altera Software (Command-Line).

2. For VHDL designs, to map to the ModelSim precompiled libraries:

   vmap <device family> \<ModelSim-Altera install directory>\altera\vhdl\<device family>\ 

   For VHDL 87-compliant designs for APEX™ 20KE devices, you must map to the \<ModelSim-Altera install directory>\altera\vhdl\apex20ke_87\ directory.

3. If your design contains the altgxb megafunction, to map to the precompiled Stratix^™ GX timing simulation model libraries type the following command at the ModelSim prompt:

   vmap stratixgx_gxb \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\stratixgx_gxb\ 
   

   If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

4. To compile the Verilog or VHDL Output File and test bench files (if you are using a test bench) into the working directory:

   For VHDL designs:

   vcom -work work <design name>.vho 
vcom -work work <test bench>.vhd 

   For Verilog designs:

   vlog -work work <design name>.v 
vlog -work work <test bench>.v 

   If you are performing a timing simulation of an ARM®-based Excalibur™ design, repeat the above commands to compile the appropriate ARM-based Excalibur simulation model and wrapper files.

5. To continue with the ModelSim-Altera simulation flow, proceed to one of the following steps:

   • 5. Perform a Timing Simulation with the ModelSim-Altera Software
   • 5. Perform a Timing Simulation with the ModelSim-Altera Software (Command-Line)

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