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To load a design and perform a timing simulation of a Verilog or VHDL design with the Model Technology^™ ModelSim^®-Altera^® (OEM) software using command-line commands: Read This First

1. If you have not already done so, perform 4. Map to Libraries and Compile Design Files with the ModelSim-Altera Software (Command-Line).

2. If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.

3. To load the design with minimum, typical, or maximum timing values, type the following commands at the ModelSim prompt:

   For VHDL designs:

   vsim -sdf(min | typ | max) /=<design name>.sdo work.<top-level design entity> 

   For Verilog designs:

   vsim -L \<ModelSim-Altera install directory>\altera\verilog\lpm\<device family> -sdf(min | typ | max) /=<design name>.sdo work.<top-level design entity> 

4. Perform the timing simulation in the ModelSim-Altera software.

Refer to ModelSim software documentation to view and the interpret results of your simulation.

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