Overviews

Commands

See Also

To map to the ModelSim^® precompiled libraries (for VHDL designs) and compile the Verilog Output Files (.vo) or VHDL Output File (.vho) and test bench files in the Model Technology^™ ModelSim-Altera^® (OEM) software:

1. If you have not already done so, perform 2. Set Up a Project with the ModelSim-Altera Software.

2. For VHDL designs, to map to the ModelSim precompiled libraries:

1. Choose New > Library (File menu). The Create a New Library dialog box appears.

2. Under Create, select a map to an existing library.

3. In the Library Name box, type the device family name.

4. In the Library Maps to box, specify the \<ModelSim-Altera install directory>\altera\vhdl\<device family>\ directory.

For VHDL 87-compliant designs for APEX™ 20KE devices, you must map to the \<ModelSim-Altera install directory>\altera\vhdl\apex20ke_87\ directory.

3. If your design contains the altgxb megafunction, to map to the precompiled Stratix^™ GX timing simulation model libraries:

   1. Choose New > Library (File menu). The Create a New Library dialog box appears.

   2. Under Create, select a new library and a logical mapping to it.

   3. In the Library Name box, type stratixgx_gxb.

   4. In the Library Maps to box, specify the \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\stratixgx_gxb\ directory.

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

4. To compile the Verilog or VHDL Output File and test bench files (if you are using a test bench) into the working directory:

   1. Choose Compile (Compile menu).

   2. In the Library list of the Compile HDL Source Files dialog box, select the work library.

   3. In the Files of Type list, select All Files (*.*), and in the Look in list, select the name of the Verilog or VHDL Output File.

   4. Click Compile.

   5. Repeat steps 4b to 4d for the test bench file (if you are using one) that instantiates the Verilog or VHDL Output File.

   6. If you are performing a timing simulation of an ARM^®-based Excalibur^™ design, repeat steps 3b to 3d to compile the appropriate ARM-based Excalibur simulation model and wrapper files.

   7. Click Done.

5. To continue with the ModelSim-Altera simulation flow, proceed to one of the following steps:

   • 5. Perform a Timing Simulation with the ModelSim-Altera Software
   • 5. Perform a Timing Simulation with the ModelSim-Altera Software (Command-Line)

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