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Commands

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To set up a project for use with the Model Technology^™ ModelSim^®-Altera^® (OEM) software:

1. If you have not already done so, perform 1. Set Up the ModelSim-Altera Working Environment.

2. If you are performing a timing simulation, to generate the Verilog Output File (.vo) or VHDL Output File (.vho):

   1. Specify EDA tool settings in the Quartus^® II software.

   2. Compile the design with the Quartus II software. More Details

   If you want to perform power estimation, make sure you turn on Generate Power Input File in the Verilog HDL/VHDL Output Settings dialog box. If you are performing a bus functional model simulation of an ARM®-based Excalibur™ design, make sure the Output Excalibur stripe as a single module/entity is turned off in the Verilog HDL/VHDL Output Settings dialog box. If you are performing a full stripe model simulation, make sure the option is turned on.

3. Start the ModelSim software.

4. To specify the project directory:

   1. Choose Change Directory (File menu).

   2. In the Choose a Directory dialog box, type the path to the project directory in the Directory Name box.

      or

      In the Look in list, select the project directory.

   3. Click Open.

   If you are performing a functional simulation, the project is the directory that contains your design files. Ilf you are performing a timing simulation, the project directory will be the <Quartus II project directory>\simulation\modelsim directory.

5. To create a new work library:

   1. Choose New > Library (File menu). The Create a New Library dialog box appears.

   2. Under Create, select a new library and a logical mapping to it.

   3. In the Library Name box, type the library name.

   4. Select the work library in the Library Maps to list.

   When you run the ModelSim software independently from the Quartus II software, you should name your library work. When you run the ModelSim software automatically from the Quartus II software, your library is automatically named ModelSim_work under the current Quartus II project directory.

6. If you are performing a bus functional model functional simulation of an ARM-based Excalibur design, generate the bus functional model simulation files.

7. If you are performing a full stripe model functional simulation of an ARM-based Excalibur design, specify the path to the Excalibur PLI models by adding the following line to the modelsim.ini file, or to the <project name>.mpf ModelSim project file, under the VSIM section after the Veriuser comments line:

   Veriuser = $MG_LIB/mti_modelsim_verilog/libmgmm.so

8. If you are performing a functional simulation, proceed to one of the following steps:

   • 3. Perform a Functional Simulation with the ModelSim-Altera Software
   • 3. Perform a Functional Simulation with the ModelSim-Altera Software (Command-Line)

9. If you are performing a timing simulation, proceed to to one of the following steps:

   • 4. Map to Libraries and Compile Design Files with the ModelSim-Altera Software
   • 4. Map to Libraries and Compile Design Files with the ModelSim-Altera Software (Command-Line)

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