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Specifies settings for the design entry/synthesis, simulation, timing analysis, board-level, or resynthesis tool you selected in the EDA tools list in the EDA Tool Settings page of the Settings dialog box (Assignments menu).
Displays one of the following dialog boxes, depending on which tool you select:
EDA Tool Input Settings dialog box for design entry/synthesis tools
VHDL Output Settings dialog box for VHDL tools
Verilog HDL Output Settings dialog box for Verilog HDL tools
IBIS Output Settings dialog box for signal integrity verification tools
Resynthesis Tool Settings dialog box for resynthesis tools
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