See Also

If you have already compiled the design, and want to specify different EDA tools settings and generate a Verilog Output File (.vo), VHDL Output File (.vhd), and Standard Delay Format Output File (.sdo) without recompiling the design, you can use the EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu).

You can also use this command to generate Stamp model files, PartMiner XML-Format Files (.xml), and IBIS Output Files (.ibs).