ASCII text files which are used as inputs to the bus functional model for performing functional and timing simulations of ARM®-based Excalibur™ designs with other EDA tools. The following are the names and functions of the bus functional model simulation files (which must be located in the <EDA simulation tool>\simulation\ directory):
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File Name
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Function
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| input.dat | An ASCII text file (with the extension .dat), used as input to the exc_bus_translate utility. This file describes the read, write, wrapping, and incremental burst options, as well as busy and idle transactions and periods of idleness that are initiated by the embedded processor core and directed to the PLD over the Stripe-to-PLD Bridge via the Stripe Master-Port |
| mastercommands.dat | An ASCII text file (with the extension .dat), created by the exc_bus_translate utility. This file describes the bus transactions between the embedded processor core and the remainder of the device over the Stripe-to-PLD Bridge via the Stripe Master-Port. The Simulator uses the data in the mastercommands.dat file to simulate the interactions between the embedded processor core and the PLD. |
| slavememory.cfg.dat | An ASCII text file (with the .dat), that specifies the start and end addresses and number of wait states for the six memory banks in the Excalibur embedded processor stripe, whose initial contents are contained in the corresponding slavememory.<bank number>.dat file for the project. The addresses of the memory banks in the memory space of the stripe must not overlap and the bank start addresses must be word-aligned. The memory spaces are used to simulate the bus transactions between the PLD and stripe memory (SDRAM Interface, Expansion Bus Interface, UART Interface, etc.) |
| slavememory.<bank number>.dat | An ASCII text file (with the .dat), which contains the initial contents of the memory bank in the Excalibur embedded processor stripe that is accessed by the PLD through the Stripe Slave-Port. The bus functional model supports up to six memory banks whose memory spaces, including start and end addresses, are specified in the slavememory.cfg.dat file. Each memory space may consist of up to 65536, little-endian, 32-bit words. The variable <bank number> is the corresponding memory bank number (0-5). |
| output.dat | An ASCII text file (with the extension .dat) generated by the bus functional model when you simulate an ARM-based Excalibur design that contains an embedded processor core in other EDA tools. This file describes the bus transactions between the embedded processor core and the PLD during simulation, via the Stripe Master- and Slave-Ports. If no slavememory.cfg.dat file or slavememory.<bank number>.dat files exist in the project directory, the bus transactions that occur on the Stripe Slave-Port are still written to the output.dat file. However, any return information from the memory banks in the stripe are set to zero. |
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