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Commands

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To compile the atom simulation model libraries, Verilog Output File (.vo) or VHDL Output File (.vho), and test bench files in the Model Technology^™ ModelSim^® PE or SE (non-OEM) software:

1. If you have knot already done so, perform 2. Set Up a Project with the ModelSim Software (Command-Line).

2. If your design contains the altgxb megafunction, to map to the precompiled Stratix^™ GX timing simulation model libraries type the following command at the ModelSim prompt:

   vmap stratixgx_gxb \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\stratixgx_gxb\ 
   

   If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

3. For VHDL designs, type the following commands at the ModelSim prompt:

   vcom -work work <path to library>\<device family>_components.vhd 
vcom -work work <path to library>\<device family>_atoms.vhd 
vcom -work work <design name>.vho 
vcom -work work <test bench>.vhd 

   For VHDL 93-compliant designs for APEX™ 20KE devices, type the following command to compile the simulation model: vcom -93 -work work <path to library>\apex20ke_atoms.vhd

4. For Verilog designs, type the following commands at the ModelSim prompt:

   vlog -work work <path to library>\<device family>_atoms.v 
vcom -work work <design name>.vo 
vcom -work work <test bench>.v 

5. To continue with the ModelSim simulation flow, proceed to one of the following steps:

   • 5. Perform a Timing Simulation with the ModelSim Software
   • 5. Perform a Timing Simulation with the ModelSim Software (Command-Line)

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