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To perform a timing simulation of a Quartus^® II–generated Verilog Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Synopsys^® VCS software:

1. If you have not already done so, perform 1. Set Up the VCS Working Environment.

2. To generate the Verilog Output File:

   1. Specify EDA tool settings in the Quartus II software.

   2. Compile the design with the Quartus II software.

   The Quartus II Compiler generates the VHDL Output File and the SDF Output File and places them in the /<project directory>/simulation/vcs directory. More Details

3. To compile the Verilog Output File with the VCS software, type one of the following commands at the command prompt:

To generate a simv.exe file, which you can use later to simulate the design: vcs <test bench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf

or

To compile the Verilog Output File with the VCS software and simulate it automatically: vcs -R <test bench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf

If your design contains the altgxb megafunction, you must also specify the stratixgx_hssi_atoms.v timing simulation library, located in the \quartus\eda\sim_lib\vcs\ directory. You must also set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

For more information about other ways to perform a timing simulation with the VCS software, or for more information about using the VCS graphical user interface, refer to the VCS User Guide.

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