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Commands

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To prepare for a functional simulation of a Verilog HDL design with the Synopsys^® VCS software, you can type a command that compiles the design and generates a simv.exe file that you can use to simulate the design. Alternatively, you can type a command that compiles and simulates the design automatically.

To perform a functional simulation of a Verilog HDL design with the VCS software by using the command line:

1. If you have not already done so, perform 1. Set Up the VCS Working Environment.

2. If the Verilog HDL design uses memory initialization data in a Hexadecimal (Intel-Format) File (.hex), to use a HEX File without the convert_hex2ver utility:

   1. Export the HEX File as a RAM Initialization File (.rif).

   2. add parameter lpm_file = "<RIF name>"; to your Verilog design file or test bench file.

3. Refer to the following table and type the appropriate command at the command prompt.

Design Type	Commands for Compiling the Design and Generating a simv.exe File	Commands for Compiling and then Automatically Simulating the Design
Verilog design without HEX File	vcs <design name>.v [<test bench>.v] -v <library file>.v	vcs -R <design name>.v [<test bench>.v] -v <library file>.v
Verilog design with HEX File and convert_hex2ver utility	vcs <design name>.v [<test bench>.v] -CC -I<path to VCS include directory> \quartus\eda\synopsys\vcs\src\ convert_hex2ver.c -v <library file>.v -P \quartus\eda\synopsys\vcs\src\ alt_pli.tab	vcs -R <design name>.v [<test bench>.v] -CC -I<path to VCS include directory> \quartus\eda\synopsys\vcs\src\ convert_hex2ver.c -v <library file>.v -P \quartus\eda\synopsys\vcs\src\ alt_pli.tab
Verilog design with HEX File and without the convert_hex2ver utility	vcs -v \quartus\eda\sim_lib\nopli.v <library file>.v <design name>.v [<test bench>.v] -	vcs -R -v \quartus\eda\sim_lib\nopli.v <library file>.v <design name>.v [<test bench>.v] -

You must enter the above commands for each source file in the design, where the <design name>.v and <test bench>.v variables may each represent one or more of the source files of the design. The <library file>.v variable may represent one or more of the functional simulation libraries. If your design contains the altgxb megafunction, you must also specify the stratixgx_mf.v functional simulation library, located in the \quartus\eda\sim_lib\vcs\ directory. Refer to the VCS User Guide for more information on the required and optional environment variables.

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

4. To continue with the VCS simulation flow, proceed to 3. Perform a Timing Simulation with the VCS Software.

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