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To perform a timing simulation of a Quartus^® II–generated Verilog Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Cadence NC-Verilog software:

1. If you have not already done so, perform 1. Set Up the NC-Verilog Working Environment.

2. To generate the Verilog Output File (.vo):

   1. Specify EDA tool settings in the Quartus II software.

   2. Compile the design with the Quartus II software.

   The Quartus II Compiler generates the Verilog Output File and the SDF Output File and places them in the /<project directory>/simulation/ncsim directory. More Details

3. Copy the cds.lib and hdl.var files, which are located in the \<NC-Verilog installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

4. Edit the cds.lib and hdl.var files as follows:

   File Name	File Contents	Function
   cds.lib	DEFINE <work library> ./work	Maps the <work library> to the physical location of the work library.
   hdl.var	DEFINE WORK <work library>	Maps the NC-Verilog variable WORK to the <work library>.

5. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix^™ GX timing simulation model libraries:

DEFINE stratixgx_gxb \quartus\eda\sim_lib\ncsim\verilog\stratixgx_gxb

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

6. Start the NC-Verilog software by typing the following command at the command prompt:

   ncdesktop 

7. To create a work library, select Add > New Library (Edit menu) and type the name of the work library in the Library box. More Details

When you run the NC-Verilog software automatically after compilation in the Quartus II software, the NC-Verilog software automatically performs steps 5 through 7.

8. To compile the appropriate project files and libraries into the work library:

   1. Choose Verilog Compiler (Tools menu).

   2. In the File box, type the path of the test bench file (if you are using one).

   3. In the Work Library list, select the work library.

   4. Click OK.

   5. Repeat steps 8a to 8d to compile the Verilog Design File (.v) for the project and the appropriate Altera^® postrouting library.

9. To elaborate the design, choose Elaborator (Tools menu) and type <work library>.<top-level entity name> in the Design Unit box.

10. To simulate the design, choose Simulator (Tools menu) and type <work library>.<top-level entity name> in the Design Unit box.

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