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To use the Cadence NC-Verilog software to perform a functional simulation of a Verilog HDL design that contains Altera-specific components:

1. If you have not already done so, perform 1. Set Up the NC-Verilog Working Environment.

2. Start the NC-Verilog software by typing ncdesktop  at a command prompt.

3. To create a work directory, select Add > New Library (Edit menu) and type the name of the work library in the Library box.  More Details

4. Copy the cds.lib and hdl.var files, which are located in the \<NC-Verilog installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

5. Edit the cds.lib and hdl.var files as follows:

   File Name	File Contents	Function
   cds.lib	DEFINE <work library> ./work	Maps the <work library> to the physical location of the work library.
   hdl.var	DEFINE WORK <work library>	Maps the NC-Verilog variable WORK to the <work library>.

6. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix^™ GX functional simulation model libraries:

DEFINE altgxb \quartus\eda\sim_lib\ncsim\verilog\altgxb

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

7. If your design contains CAM, RAM, or ROM functions, and you are using a Hexadecimal (Intel-Format) File (.hex), to convert the memory initialization data without using the convert_hex2ver utility:

   1. Export the HEX File as a RAM Initialization File (.rif) in the Quartus^® II software.

   2. Add the text parameter lpm_file = "<RIF name>.rif"; for the CAM, RAM, or ROM function to your top-level design or test bench file.

   3. Choose Verilog Compiler (Tools menu).

   4. In the Compile Verilog dialog box, turn on Define Macro and type NO_PLI in the box.

   5. Click Apply.

8. If your design contains CAM, RAM, or ROM functions, and you are using a HEX File, to specify that the NC-Verilog software should use the convert_hex2ver utility to convert the HEX File:

1. Build the convert_hex2ver utility.

2. Choose Advanced Options > Elaborator (Tools menu). The Elaborator Advanced Options dialog box appears.

3. Select Programming Language Interface.

4. Turn on Dynamically Load PLI Library and type the path and name of the convert_hex2ver you created in step 7a.

9. To compile the appropriate project files and libraries into the work library:

   1. Choose Verilog Compiler (Tools menu).

   2. In the File box, type in the path of the test bench file (if you are using one).

   3. In the Work Library list, select the work library.

   4. Click OK.

   5. Repeat steps 8a through 8d to compile the Verilog Design File (.v) for the project and the appropriate Altera^® prerouting library.

10. To elaborate the design, select Elaborator (Tools menu) and type <work library>.<top-level entity name> in the Design Unit box.

11. To continue with the NC-Verilog simulation flow, proceed to one of the following steps:

    • 3. Perform a Timing Simulation with the NC-Verilog Software
    • 3. Perform a Timing Simulation with the NC-Verilog Software (Command-Line)

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