eda

3. Perform a Timing Simulation with the NC-Verilog Software (Command-Line)

To perform a timing simulation of a Quartus® II–generated Verilog Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Cadence NC-Verilog software, using command-line commands:

  1. If you have not already done so, perform 1. Set Up the NC-Verilog Working Environment.

  2. To generate the Verilog Output File (.vo):

    1. Specify EDA tool settings in the Quartus II software.

    2. Compile the design with the Quartus II software.

    NOTE The Quartus II Compiler generates the Verilog Output File and the SDF Output File and places them in the /<project directory>/simulation/ncsim directory. More Details

  3. Create a work library in the project directory by typing the following command at the command prompt: More Details

    4. mkdir <work library> Enter

  4. Copy the cds.lib and hdl.var files, which are located in the \<NC-Verilog installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

  5. Edit the cds.lib and hdl.var files as follows:

    File Name File Contents Function
    cds.lib

    DEFINE <work library> ./work

    Maps the <work library> to the physical location of the work library.
    hdl.var

    DEFINE WORK <work library>

    Maps the NC-Verilog variable WORK to the <work library>.

  6. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix™ GX timing simulation model libraries:

    7. DEFINE stratixgx_gxb \quartus\eda\sim_lib\ncsim\verilog\stratixgx_gxb

    NOTE If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

    NOTE When you run the NC-Verilog software automatically after compilation in the Quartus II software, the NC-Verilog software automatically performs steps 4 and 5.

  7. To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:

    8. ncvlog <test bench file> Enter
    ncvlog <project name>.vo Enter
    ncvlog \quartus\eda\sim_lib\ <device family>_atoms.v Enter

  8. To elaborate and simulate the design, type the following commands at the command prompt:

    9. ncelab <work library>.<top-level entity name> Enter
    ncsim <work library>.<top-level entity name> Enter


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