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To perform resynthesis on a Quartus^® II design with the ADT PALACE software:

1. If you have not already done so, perform 1. Set Up the PALACE Working Environment.

2. Create a new project or open an existing project.

3. To generate the output files for resynthesis in the PALACE software:

   1. Specify EDA tool settings in the Quartus II software.

   2. Compile the design with the Quartus II software.

   The Quartus II Compiler generates a Verilog Quartus® Mapping File (.vqm) and places it in the /<project directory>/resynthesis/adt directory, with the appropriate settings and configurations files and the <design name>.pc and <design name>.tc files, which contain user-specified pin and timing constraints.

4. The Quartus II software launches the PALACE software, which performs resynthesis on the design. The PALACE software generates an optimized <design name>_adt.vqm VQM File and launches the Quartus II software to compile the optimized design in the /<project directory>/resynthesis/adt directory.

When the Quartus II software compiles the optimized design, it displays the System tab of the Messages window. To view the status of the compilation, click the Processing tab.

5. You can view the optimized design in the Quartus II software. To compare it with the original project, open the project in the original project directory.

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