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You can generate an IBIS Output File (.ibs) in the Quartus^® II software to perform board-level signal integrity verification in other EDA tools.

IBIS model generation is fully supported for all devices supported by the Quartus II software, except Cyclone™ and Stratix™ GX devices. For additional IBIS model device support and support files, refer to IBIS models in the Device Support section on the Altera® web site.

To generate an IBIS Output File:

1. Create a new project or open an existing project.

2. Specify EDA tool settings. Make sure you select Signal Integrity (IBIS) in the Board-level tool list of the EDA Tool Settings page of the Settings dialog box (Assignments menu).

3. If necessary, specify the output settings for the IBIS Output File by clicking Settings in the EDA Tool Settings page of the Settings dialog box (Assignments menu).

4. To generate the IBIS Output File, compile the design.

The Quartus II software places the IBIS Output File in the \<project name>\board\ibis directory. If you have already compiled the design, and want to specify different EDA tools settings and generate output files without recompiling the design, you can use the EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu).

5. Use the IBIS Output File to perform board-level signal integrity verification in the Mentor Graphics^® Interconnect Synthesis, Innoveda XTK and HyperLynx, and Cadence SPECCTRAQuest software.

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