EDA Interfaces

5. Generate Verilog Quartus Mapping Files with the Synplify Software

To generate Verilog Quartus® Mapping Files (.vqm) in the Synplicity Synplify software for use with the Quartus® II software:

  1. If you have not already done so. perform 4. Assign Design Constraints with the Synplify Software.

  2. To run the Synplify software, click Run. The Synplify software synthesizes and optimizes the design, and creates a VQM File.

  3. Correct any errors or warnings.

  4. If you have corrected errors or warnings, or added timing requirements to your design, repeat step 2 to run the Synplify software and implement the changes in the Synplify-synthesized design.

    5. NOTE Altera® recommends that you store the result file in a separate directory from the source files. Be sure that any VHDL or Verilog HDL files (or black boxes) are also copied to this directory.

  5. Create the \<project directory>\quartus directory.

  6. Copy the <design name>.vqm, <design name>.tcl and black box files generated in step 2 to the \<project directory>\quartus directory.

  7. After creating and loading the project in the Quartus II software, run the Synplify-generated TCL Script File in the Quartus II software.

  8. Compile the design with the Quartus II Compiler.

  9. To continue with the Synplify design flow, proceed to 6. Analyze Design Results with the Synplify Software.


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