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Assigning design constraints in the Synplicity Synplify software includes specifying pin assignments, timing constraints, and other resource assignments. When you use the Synplify software, you can assign a limited subset of Quartus^® II resource assignments by specifying attributes in the Synplify Design Constraints File (.sdc) or in the VHDL or Verilog HDL design files. The Synplify software automatically incorporates these attributes into a <design>.tcl file targeted to any Altera^® device supported by the Quartus II software. If you add timing constraints or resource assignments in a separate Synplify Design Constraints File, you must add the Synplify Design Constraints File to the project by adding it to the Source Files list in the Synplify window.

To specify design constraints in the Synplify software:

1. If you have not already done so, perform 3. Set Up a Project in the Synplify Software.

2. You can assign a single port to a specific pin to ensure that the signal is always associated with that pin, regardless of future changes to a project. You can specify pins in VHDL or Verilog HDL designs, or in a Synplify Design Constraints File (.sdc). To make pin assignments using the Synplify software:

   1. Open the SCOPE file.

   2. Click the Attributes tab.

   3. Select the pin for which you wish to make the assignment in the Object column.

   4. Select altera_chip_pin_lc in the Attribute column.

   5. Enter a pin name in the Value column.

   Refer to the following table for the correct syntax on making pin assignments in Verilog and VHDL design files and Synplify Design Constraints Files:

   File Type	Syntax
   VHDL	attribute altera_chip_pin_lc : string; attribute altera_chip_pin_lc of <port name> : signal is "@<pin number(s)>"; Example: attribute altera_chip_pin_lc : string; attribute altera_chip_pin_lc of result : signal is "@17, @166, @191, @152, @15, @148, @147, @149";
   Verilog HDL	<port name> /* synthesis altera_chip_pin_lc="@<pin number(s)>" */; Example: output [7:0] sum /* synthesis altera_chip_pin_lc="@17, @166, @191, @152, \ @15, @148, @147, @149" */;
   Synplify Design Constraints File	define_attribute <port name> altera_chip_pin_lc "@<pin number>" Example: define_attribute {DATA0[7:0]} altera_chip_pin_lc "@115,@116,@117, @118,@119,@120,@121,@122"

3. Add appropriate timing constraints in a separate Synplify Design Constraints File (.sdc) or in the VHDL or Verilog HDL source file. If you add timing constraints or resource assignments in a separate SDC file, you must add the SDC file to the Source Files list in the Synplify window by using the Scope option. Synplify incorporates attributes that are applicable to the Quartus II software into a <design name>.tcl file that can be read by the Quartus II software.

   You can specify the f_MAX timing requirement in the Synplify software and add the DEFINE_INPUT_DELAY and DEFINE_OUTPUT_DELAY variables in the SDC File. The Synplify software then uses the values in the SDC File when it creates the <design name>.tcl file.

4. To continue with the Synplify design flow, proceed to 5. Generate Verilog Quartus^® Mapping Files with the Synplify Software.

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