Procedures

Commands

See Also

You can use the Synplicity Synplify design entry/synthesis tool to create, synthesize, and optimize a project and then generate an Verilog Quartus^® Mapping File (.vqm) for compilation in the Quartus^® II software. The following steps describe the typical flow to create, synthesize, and optimize a project, and generate a VQM File:

1. Set up the Synplify Working Environment

2. Create a Design for Use with the Synplify Software

3. Set Up a Project with the Synplify Software

4. Assign Design Constraints with the Synplify Software

5. Generate Verilog Quartus Mapping Files with the Synplify Software

6. Analyze Design Results with the Synplify Software

You can use Altera-provided megafunctions in the Synplify software by using the MegaWizard^® Plug-In Manager (Tools menu) to create custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions and Altera^® megafunctions. Refer to the following topics for information on how to use specific megafunctions. You can use the same procedures and principles to use similar megafunctions in other designs.

• Creating & Instantiating a VHDL Function for Use with the Synplify Software

• Creating & Instantiating a Verilog HDL Function for Use with the LeonardoSpectrum^™ Software

More information is available on other EDA design entry/synthesis tools on the Altera web site.

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