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You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the Synplicity Synplify and Quartus^® II software. This procedure shows only how to instantiate a ClockLock^® PLL function using VHDL; however, you can use similar procedures to instantiate other Altera-provided functions.

If you want to use the lpm_mult, lpm_ram_dp, lpm_ram_dq, lpm_rom, lpm_latch, or lpm_ff library of parameterized modules (LPM) functions, refer to Create a Design for Use with the Synplify Software.

1. If you have not already done so, proceed to Set Up the Synplify Working Environment.

2. If you have not already done so, proceed to Create a Design for Use with the Synplify Software.

3. Open the MegaWizard^® Plug-In Manager (Tools menu) and specify appropriate options for your the megafunction you want to instantiate.

The MegaWizard Plug-In Manager generates custom megafunction variations that are based on Altera-provided functions, including library of parameterized modules (LPM) functions, as well as Altera^® megafunctions.

Refer to the following example to create a VHDL custom megafunction variation of the altclklock function:

• Example of Creating a VHDL Custom Variation of the altclklock Function.

4. To prepare the VHDL design for synthesis with the Synplify software, you must specify that the Synplify software should treat the design file created in the MegaWizard Plug-In Manager as a "black box." The Synplify software then makes the correct connections to the ports in the Verilog HDL netlist file (.vqm). The Quartus II software reads in the Verilog HDL netlist file as a Verilog Quartus II Mapping File (.vqm) and processes the instantiated megafunction. If you are using Synplicity Synplify version 5.22 or later software, the Synplify software automatically treats all components that do not have behavioral descriptions as black boxes and you do not need to modify the source file.To specify that the Synplify software should treat the design file for the megafunction as a "black box," refer to the following example:

• Example of Creating a "Black Box" for a Verilog HDL Custom Variation of a Megafunction with the Synplify Software.

The design file generated by the MegaWizard Plug-In Manager must be in the same directory as the VQM File or added to the Quartus II project.

5. If necessary, perform a functional simulation of the design using an EDA simulation tool. Refer to the following example for a sample script used in performing a functional simulation:

• Example of Performing a Functional Simulation of a Synplify VHDL Design with a Custom Megafunction Variation with the ModelSim^® Software.

6. Proceed to Generate Verilog Quartus^® Mapping Files with the Synplify Software.

7. If you have not already done so, create a new project or open an existing project.

8. Compile the design in the Quartus II software.

9. If necessary, proceed to Perform a Timing Simulation with the ModelSim Software or simulate the design with another Verilog HDL simulation tool. Refer to to the following example for a sample script that you can use to perform the timing simulation:

• Performing a Timing Simulation of a Synplicity VHDL Design with a Custom Megafunction Variation with the ModelSim Software.

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