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You can create Verilog HDL design files with the Quartus^® II Text Editor or another standard text editor for use with the Synplicity Synplify software.

To create a Verilog or VHDL design for use with the Synplify software:

1. If you have not already done so, perform 1. Set Up the Synplify Working Environment

2. Enter a VHDL or Verilog HDL design in the Quartus II Text Editor or another standard text editor and save it in your working directory. Only describe the design with Verilog or VHDL; the Synplify software cannot synthesize Block Design Files (.bdf) or other proprietary Altera^® formats.

When connecting ports in the Verilog Design File, make sure you connect ports by name instead of by order. When generating Verilog Output Files (.vo) from imported VQM Files for simulation in other EDA simulation tools, the Quartus II software does not retain the order of ports.

3. To use megafunctions in the design, use the MegaWizard^® Plug-In Manager (Tools menu) to generate and instantiate a megafunction variation. You can use the MegaWizard Plug-In Manager to create content-addressable memory (CAM), ClockLock^® PLL, LVDS, and RAM functions. The following topics show how to create and instantiate some of these functions:

• Creating & Instantiating a Verilog HDL ClockLock PLL Function for Use with the Synplify Software
• Creating & Instantiating a VHDL ClockLock PLL Function for Use with the Synplify Software

4. If you want to use the lpm_mult, lpm_ram_dp, lpm_ram_dq, lpm_rom, lpm_latch, or lpm_ff library of parameterized modules (LPM) functions, for which the Synplify software (version 7.0 and later) has timing models for critical path timing estimates, you can use the MegaWizard Plug-In Manager to create the LPM functions and then instantiate them in your design.

To create and instantiate an LPM function in your design:

1. Open the MegaWizard Plug-In Manager (Tools menu) and specify the appropriate options for the LPM function you want to create. The MegaWizard Plug-In Manager creates a Verilog Design File (.v) or a VHDL Design File (.vhd) for the function.

2. Instantiate the function in your design, including the parameters and omitting the syn_black_box directive in the module or entity for that function. You must then add the Verilog Design File or VHDL Design File to your project in the Synplify software, so the Synplify software synthesizes it and includes it in the VQM File for the project.

3. When creating the project in the Synplify software, for Verilog HDL designs, you must also add the altera_lpm.v file, which is located in the <Synplify system directory>\lib\altera directory. For VHDL designs, add the following statement to the design file:

library lpm;
use lpm.lpm_components.all;

5. Instantiate any Quartus II–supported logic functions in the Verilog HDL design. You can enter the following functions:

   • Parameterized and non-parameterized megafunctions. The Quartus II software also supports all functions in the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions.

   • Buffer primitives, including lcell, soft, global, carry, and cascade. The Synplicity altera.v and altera.vhd libraries provide synthesis support for these functions.

   • MegaCore^® functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP^SM). The OpenCore^® feature in the Quartus II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and postcompilation simulation support.

6. If your VHDL design uses functions from the altera.vhd library, add the following Library and Use clauses to the top of a file that instantiates the macrofunction(s):

   library altera;
use altera.maxplus2.all;

7. For each Quartus II–supported logic function, include a syn_black_box synthesis directive. You can omit this step for functions from the altera.v and altera.vhd libraries.

8. For any parameterized function, declare all parameters used in the function, their types, and their values. The following examples show a Verilog HDL and VHDL file that instantiates the lpm_ram_dq function.

   • Example of a Verilog Design File with LPM Function Instantiation
   • Example of a VHDL Design File with LPM Function Instantiation

9. To continue with the Synplify design flow, proceed to 3. Set Up a Project with the Synplify Software.

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