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Commands

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Setting up a project in the Synplify software includes starting the Synplify software, creating the project and adding files, and selecting a target device and output settings. To setup a project in the Synplify software:

1. If you have not already done so, perform 2. Create a Design for Use with the Synplify Software.

2. To start the Synplify software on a UNIX workstation, type synplify at a command prompt from your working directory.

   or

   To start the Synplify software on a PC, type synplify at a command prompt, or double-click the synplify.exe icon.

3. To create and add files to a new project:

1. Choose New (File menu). The New dialog box appears.

2. In the File Type list, select Project File (Project).

3. Click OK.

4. In the Project window, click Add.

5. In the Select Files to Add to Project dialog box, select one or more design files to add to the project.

6. To add the file(s) in the Files To Add To Project list in the Synplify window, click Add.

To create a hierarchical project, select the top-level design file in the Files to Add to Project list and drag it to the bottom of the list. If you created and instantiated an LPM function in your design, you must also include the Verilog Design File or VHDL Design File generated by the MegaWizard Plug-In Manager in your project.

7. Click OK.

4. If the design uses functions from the altera.v library, add the library file name to the top of the Source Files list in the Synplify window.

5. To select the target Altera device:

   1. In the Target section, click Change. The Options for implementation dialog box appears.

   2. Click the Device tab.

   3. In the Technology list, select the device family.

   4. In the Part list, select a device name.

   5. In the Speed list, select an appropriate speed grade.

   6. In the Package list, select the device package

   7. Under Device Mapping Options, turn on Map logic cells to ATOMS.

6. To specify output settings:

1. Click the Implementation Results tab.

2. To specify the format for Synplify-generated output files, select vqm in the Result Format box. For Synplicity Synplify version 6.0 and later, the output files are generated by default into the rev_1 directory.

3. To change the results directory, type the name of the new directory in the Results Directory box.

4. Click OK.

7. Type the frequency value for the project in the Frequency (MHz) box in the Synplify window.

8. To direct the Synplify software to automatically find and re-encode state machines in your design, turn on Symbolic FSM Compiler in the Synplify window. Turning on this option may reduce unnecessary states and transitional logic.

9. Turn on Resource Sharing in the Synplify window. This option decreases area but might also decrease performance.

10. To continue with the Synplicity design flow, proceed to 4. Assign Design Constraints with the Synplify Software.

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