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You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the Synplicity Synplify and Quartus^® II software. This procedure shows only how to instantiate a content-addressable memory (CAM) function using Verilog HDL; however, you can use similar procedures to instantiate other Altera-provided functions.

1. If you have not already done so, Set Up the LeonardoSpectrum^™ Working Environment.

2. If you have not already done so, Create a Design for Use with the LeonardoSpectrum Software.

3. Open the MegaWizard^® Plug-In Manager (Tools menu) and specify appropriate options for the megafunction you want to instantiate.

   The MegaWizard Plug-In Manager generates custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions, as well as Altera^® megafunctions.

   See the following example to create a Verilog HDL custom megafunction variation of the altcam function:

   • Example of Creating a Verilog HDL Custom Variation of the altcam Function.

4. To prepare the Verilog HDL design for synthesis with the LeonardoSpectrum software, you must specify that the LeonardoSpectrum software should treat the design file created in the MegaWizard Plug-In Manager as a "black box." The LeonardoSpectrum software then makes the correct connections to the ports in the EDIF netlist file (.edf). The Quartus II software reads in the EDIF netlist file as an EDIF Input File (.edf) and processes the instantiated megafunction. The LeonardoSpectrum software automatically treats all modules that do not have behavioral descriptions as black boxes. For an example on how to add an empty module declaration to a Verilog Design File, refer to the following example:

• Example of Creating a "Black Box" for a Verilog HDL Custom Megafunction Variation Using the LeonardoSpectrum Software.




The design file generated by the MegaWizard Plug-In Manager must be in the same directory as the EDIF Input File or added to the Quartus II project.

5. If necessary, perform a functional simulation of the design using an EDA simulation tool. Refer to the following example for a sample script used in performing a functional simulation:

• Example of Performing a Functional Simulation of a Verilog HDL Design with a Custom Megafunction Variation with the ModelSim^® Software.

6. If you have not already done so, create a new project or open an existing project.

7. Continue to Generate EDIF Netlist Files with the LeonardoSpectrum Software.

8. Compile the design in the Quartus II software.

9. If necessary, perform a timing simulation of the design with the ModelSim software or with another Verilog HDL simulation tool.

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