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You can use the optional Synplify HDL Analyst to analyze and evaluate the performance of a design graphically. The Synplify HDL Analyst generates Register Transfer Level (RTL) schematics, as well as technology-mapped, gate-level schematics. You can instantly identify and fix potential problems earlier in the design cycle by cross-probing between the RTL schematics, gate-level schematics, and HDL source code. The Synplify HDL Analyst also highlights critical paths within the design to show which signals require optimization for performance. After you determine the critical speed paths, you can add timing constraints either to the VHDL or Verilog HDL source file or to a separate Synplify Design Constraints File (.sdc) to improve design performance. You can also use the Synplify HDL Analyst to cross-probe nodes in the Synplify HDL Analyst with the corresponding nodes in the Quartus^® II Floorplan Editor.

To use the Synplify HDL Analyst after synthesizing your design with Synplify software, go through the following steps:

1. If you have not already done so, perform 5. Generate Verilog Quartus^® Mapping Files with the Synplify Software.

2. Choose an HDL Analyst view:

Choose RTL View (HDL_Analyst menu) to view the RTL schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (+) symbol.

or

Choose Technology View (HDL_Analyst menu) to view the gate-level schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (+) symbol.

3. To use the Synplify HDL Analyst to cross-probe nodes between the Synplify and Quartus II software, select External Cross Probing Engaged (HDL Analyst menu) in the Synplify software and enable cross-probing in the Quartus II software.

4. In either the RTL or Technology View, perform one or more of the following actions:

• Click the plus (+) symbol pointer on a port name or symbol to highlight the node in the Quartus II Floorplan Editor.
• Double-click the plus (+) symbol pointer on a port name or symbol to cross-probe your VHDL or Verilog HDL source design files in the Synplify software.

Because the Synplify software combines the a + b and a - b operations, cross-probing highlights the Case Statement that defines both functions.

• Choose Find (HDL_Analyst menu) to select specific signals quickly in your design.
• Choose Show Critical Path (HDL_Analyst menu) to highlight the critical paths in the design.
• Choose Filter Schematic (HDL_Analyst menu) to show only the nodes you have selected.

5. You can also highlight nodes in the Quartus II Floorplan Editor to cross-probe the corresponding nodes in the Synplify HDL Analyst.

6. To continue with the Synplify design flow, return to 5. Generate Verilog Quartus Mapping Files with the Synplify Software.

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