Overviews

Commands

See Also

The Quartus^® II Compiler can process a VHDL or Verilog HDL file that the Synopsys^® Design Compiler software synthesized, saved as an EDIF 2 0 0 netlist file, and imported into the Quartus II software.

To synthesize and optimize a VHDL or Verilog HDL design with the Design Compiler software for use with the Quartus II software:

1. If you have not already done so, perform 3. Create a Design for Use with the Design Compiler Software.

2. To start the Design Compiler software and to work within the graphical user interface, type the following commands at the command prompt:

dc_shell 
design_analyzer 

3. Analyze and then compile the design with the Design Compiler or Design Analyzer software. The VHDL Compiler or HDL Compiler for Verilog software automatically translates the design into Synopsys database (.db) format. For some types of projects, you must follow these steps before you process the design:

1. If you are compiling an ACEX^® 1K, APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, Cyclone^™, FLEX 10KE, Mercury^™, Stratix^™, and Stratix^™ GX designs, that includes RAM or ROM functions:

1. (VHDL designs only) Because the VHDL Compiler software does not support the data type string for the Generic Clause, enter the following command at the dc_shell prompt before you read the design:

hdlin_translate_off_skip_text=true

2. The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information the Design Compiler software can use. Add this timing model to the existing library so that the compiler can access the timing information. Refer to the following table and type one of the commands at the dc_shell prompt:

Device Family	Commands for Adding Timing Models to the Existing Libraries
ACEX 1K	read -f db acex1k.db update_lib acex1k <RAM/ROM function name>.lib
APEX 20K	read -f db apex20k-3.db update_lib apex20k-3 <RAM/ROM function name>.lib
APEX 20KC	read -f db apex20kc-3.db update_lib apex20kc-3 <RAM/ROM function name>.lib
APEX 20KE	read -f db apex20ke-3.db update_lib apex20ke-3 <RAM/ROM function name>.lib
APEX II	read -f db apexii-3.db update_lib apexii-3 <RAM/ROM function name>.lib
Cyclone	read -f db cyclone.db update_lib cyclone <RAM/ROM function name>.lib
FLEX 10KE and ACEX 1K	read -f db flex10ke-3.db update_lib flex10ke-3 <RAM/ROM function name>.lib
Mercury	read -f db mercury-3.db update_lib mercury-3 <RAM/ROM function name>.lib
Stratix	read -f db stratix-3.db update_lib stratix-3 <RAM/ROM function name>.lib
Stratix GX	read -f db stratixgx.db update_lib stratixgx <RAM/ROM function name>.lib

3. (Optional) To update the flex10k[<speed grade>].db file with the RAM/ROM timing information, refer to the following table and type one of the commands at the dc_shell prompt:

Device Family	Commands for Updating the flex10k[<speed grade>].db file with the RAM/ROM Timing Information
ACEX 1K	write_lib acex1k -o acex1k.db
APEX 20K	write_lib apex20k-3 -o apex20k-3.db
APEX 20KC	write_lib apex20kc-3 -o apex20kc-3.db
APEX 20KE	write_lib apex20ke-3 -o apex20ke-3.db
APEX II	write_lib apexii-3 -o apexii-3.db
Cyclone	write_lib cyclone -o cyclone.db
FLEX 10KE and ACEX 1K	write_lib flex10ke-3 -o flex10ke-3.db
Mercury	write_lib mercury-3 -o mercury-3.db
Stratix	write_lib stratix-3 -o stratix-3.db
Stratix GX	write_lib stratixgx -o stratixgx.db

See Instantiating RAM & ROM Functions in VHDL or Instantiating RAM & ROM functions in Verilog HDL for additional information.

2. (Optional) Enter resource assignments. The Quartus II software allows you to make a variety of resource and device assignments for projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded System Block (ESB), Embedded Array Block (EAB), MegaLAB^™ structure, row, column, fast region, custom region, section, chip, clique, local routing, logic option, or timing assignments or requirements. In the Quartus II software, you can enter all types of resource and device assignments with the Assignment Organizer. You can also enter assignments in the Quartus II Floorplan Editor.

For additional information on how the Design Compiler synthesizes and optimizes a design, refer to the Synopsys Design Compiler Reference Manual or Design Analyzer Reference Manual.

4. (Optional) View the optimized design with the Design Analyzer. The Design Analyzer uses the altera.sdb library to display optimized designs generated by the Design Compiler.

5. (Optional) To view Synopsys-generated timing information and generate a file detailing primitive usage, type the following commands at the dc_shell prompt:

report_timing 
report_reference > <filename> 

6. Specify EDA tool settings and compile the design in the Quartus II software.

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