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You can create Verilog HDL design files with the Quartus^® II Text Editor or another standard text editor for use with the Synopsys^® Design Compiler software.

To create a Verilog or VHDL design for use with the Design Compiler software, follow these steps:

1. If you have not already done so, perform 1. Set up the Design Compiler Working Environment.

2. Instantiate logic functions with a Component Instantiation, and include a Module Declaration (Verilog) or Component Declaration (VHDL) for each function. Altera^® provides simulation models for the following types of logic functions:

• Primitives in the Design Compiler Technology Libraries or other Altera macrofunction or non-parameterized megafunction for which no simulation models or technology library support is available. These functions are treated as "black boxes" during processing with the Design Compiler. The following examples show how to instantiate these primitives or megafunctions:

• Primitive & Old-Style Macrofunction Instantiation Example for VHDL
• Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL

If you instantiate a "black box" logic function for which no simulation/techology library support is available, create a hollow-body design description in order to prevent the Design Compiler from issuing a warning message. If you instantiate a "black box" logic function, you must create a Library Mapping File (.lmf) to map the function to an equivalent Quartus II function before you compile the project with the Quartus II software.

• Architecture Control Logic functions in the alt_mf library, which includes the a_8count, a_8mcomp, a_8fadd, and a_81mux functions. The following examples show how to instantiate these primitives:
  • Quartus II Architecture Control Logic Function Instantiation Example for VHDL
  • Quartus II Architecture Control Logic Function Instantiation Example for Verilog HDL

• For VHDL designs, the DesignWare up/down counter function (DW03_updn_ctr). Refer to DesignWare Up/Down Counter Function Instantiation Example for VHDL for an example.

• RAM and ROM functions generated with the genmem utility. The following examples show how to instantiate RAM and ROM functions using the genmem utility.
  • Instantiating RAM & ROM Functions in VHDL
  • Instantiating RAM & ROM Functions in Verilog HDL

• MegaCore^® functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP^SM). The OpenCore^® feature in the Quartus II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and postcompilation simulation support.

3. To continue with the Design Compiler design flow, continue to 4. Synthesize & Optimize a Design with the Design Compiler Software.

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