See Also

You can instantiate the Quartus^® II primitives listed in Design Compiler Technology Libraries in VHDL designs. These primitives can be used to control synthesis in the Quartus II software. You can also instantiate Quartus II megafunctions and old-style macrofunctions.

Unlike other logic functions, Quartus II primitives do not need to be defined with Component Declarations unless you wish to simulate the design with the VHDL System Simulator (VSS) software. Any references to these primitives are resolved by the Synopsys^® compilers. All buffer primitives except the ATRIBUF and TRIBUF primitives also have a "don't touch" attribute already assigned to them, which prevents the Synopsys compilers from optimizing them. The Synopsys compilers also automatically treat mega- and macrofunctions that do not have corresponding synthesis library models as "black boxes."

Figure 1 shows a 4-bit full adder with registered output that also instantiates an AGLOBAL or GLOBAL primitive. This figure also illustrates the use of global Clock and global Reset pins in the MAX^® 7000 architecture. The design uses an old-style 7483 macrofunction, which is represented as a hollow body named fa4.

Figure 1. 4-Bit Adder Design with Registered Output (adder.vhd)

LIBRARY ieee;
   USE ieee.std_logic_1164.ALL;

   ENTITY adder IS
   PORT (a, b     : IN  STD_LOGIC_VECTOR(4 DOWNTO 1);
         clk, rst : IN  STD_LOGIC;

         cout     : OUT STD_LOGIC;
         regsum   : OUT STD_LOGIC_VECTOR(4 DOWNTO 1));
   END adder;

ARCHITECTURE MAX7000 OF adder IS

SIGNAL sum            : STD_LOGIC_VECTOR(4 DOWNTO 1);
SIGNAL ci, gclk, grst : STD_LOGIC;

-- Component Declaration for GLOBAL primitive

COMPONENT global
   PORT (a_in      : IN  STD_LOGIC; 
         a_out     : OUT STD_LOGIC);
END COMPONENT;

-- Component Declaration for fa4 macrofunction
COMPONENT fa4
   PORT (c0,a1,b1,a2,b2,a3,b3,a4,b4 : IN  STD_LOGIC;
         s1,s2,s3,s4,c4             : OUT STD_LOGIC);
END COMPONENT;

BEGIN
   ci <= '0';

-- FA4 Component Instantiation
   u0: fa4 

   PORT MAP (ci,a(1),b(1),a(2),b(2),a(3),b(3),a(4),b(4),
             sum(1),sum(2),sum(3),sum(4),cout);

-- GLOBAL Component Instantiation for Clock 

   u1: global 
   PORT MAP (clk, gclk);

-- GLOBAL Component Instantiation for Reset 
-- For FLEX® devices, global should be replaced with aglobal
   u2: global
   PORT MAP (rst, grst);

-- CLOCK process to create registered output 
   clocked: PROCESS(gclk,grst)

   BEGIN
      IF grst = '0' THEN
      regsum <= "0000";

      ELSIF gclk'EVENT AND gclk = '1' THEN
            regsum <= sum;
      END IF;

   END PROCESS clocked;

END MAX7000;

Before you can analyze the 4-bit adder design, you must first analyze the fa4 description in Figure 1 with the Synopsys VHDL Compiler software. You can ignore the warning that is issued for any unknown function, including the fa4 function in this example. If you wish, you can avoid receiving such warning messages by creating a hollow-body description of the function.

A hollow-body VHDL description combines an Entity Declaration with an empty or null Architecture Body. An empty Architecture Body contains the ARCHITECTURE IS clause, followed by the BEGIN and END keywords and a semicolon (;). It does not include any information about the design's function or operation. Figure 2 shows the hollow-body description for the fa4 function.

LIBRARY ieee;
USE     ieee.std_logic_1164.ALL;

-- fa4 maps to 7483. The interface names do not have to match.

ENTITY fa4 IS

PORT (c0,a1,b1,a2,b2,a3,b3,a4,b4 : IN STD_LOGIC;
      s1,s2,s3,s4,c4             : OUT STD_LOGIC);

END fa4;

ARCHITECTURE map7483 OF fa4 IS

BEGIN

-- This architecture body is left blank, and will map to the  
-- 7483 macrofunction in Quartus II.

END;

When you analyze the hollow-body design description with the Synopsys VHDL Compiler software, it produces a hollow-body component that contains a single level of hierarchy with input and output pins, but does not contain any underlying logic.

You can save the synthesized design as an EDIF netlist file (.edf) and compile it with the Quartus II software. After the VHDL Compiler software has successfully processed the design, it generates the schematic shown in Figure 3, which you can view with the Design Analyzer software.

Figure 3. Synthesized Design Generated by the Design Compiler

However, before you compile the EDIF netlist file with the Quartus II software, you must create the adder.lmf file, shown in Figure 3, to map the fa4 function to the equivalent Quartus II function (7483). You must then specify the LMF as LMF #2 in the expanded EDIF Netlist Reader Settings dialog box (Interfaces menu) (LMF #1 is altsyn.lmf). For more information about creating LMFs, refer to "Library Mapping Files (.lmf)" and "Library Mapping File Format" in Quartus II Help.

BEGIN
FUNCTION 7483  (c0, a1, b1, a2, b2, a3, b3, a4, b4,)
RETURNS        (s1, s2, s3, s4, c4)

FUNCTION "fa4" ("c0", "a1", "b1", "a2", "b2", "a3",
               "b3","a4", "b4")
RETURNS        ("s1", "s2", "s3", "s4", "c4")
END

When you compile the design with the Quartus II software, you can disregard the warning "EDIF cell <name> already has LMF mapping so CONTENTS construct has been ignored". To verify the global Clock and global Reset usage, as well as the number of logic cells used, see the adder.rpt Report File generated by the Quartus II Compiler.

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