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To use the Quartus^® II software with Synopsys^® software, you must first install the Quartus II software, then establish an environment that facilitates entering and processing designs by modifying your Synopsys configuration files. The Quartus II/Synopsys interface is installed automatically when you install the Quartus II software on your workstation.

To set up the Design Compiler working environment:

1. Make sure you have the following versions of the Quartus II software and the Design Compiler software:

The following software applications are used to generate, process, synthesize, and verify a project with the Quartus II and Synopsys software:

Synopsys	Altera®
Design Compiler version 2002.02	Quartus II version 2.2

This version of the Design Compiler software supports all Altera devices supported by the Quartus II software except ARM^®-based Excalibur^™ devices. Compilation with the Synopsys Design Compiler is available only on Sun SPARCstations running Solaris 2.4 or higher.

The Quartus II Software Release Notes are available on the Altera web site and provide up-to-date information on which versions of Synopsys applications are supported by the current version of the Quartus II software. The Quartus II readme.txt file provides information on installation and operating requirements. You should read the Release Notes and readme.txt file before installing the Quartus II software. After installation, you can open the Release Notes and readme.txt file from the Quartus II Help menu.

2. Make sure the appropriate Quartus II/Synopsys interface directories are installed, as shown in the following table:

The following table shows the Quartus II/Synopsys interface subdirectories that are created in the Quartus II system directory (by default, the /usr/quartus directory) during the Quartus II software installation. For information on the other directories that are created during the Quartus II software installation, see "Quartus II File Organization" in the Quartus II Installation & Licensing for PCs or Quartus II Installation & Licensing for UNIX and Linux workstations manuals.

Quartus II Directory Organization
Directory	Description
./eda/synopsys/bin	Contains script programs to analyze Synopsys DesignWare models and Altera-provided macrofunctions.
./eda/synopsys/examples	Contains sample files.
./eda/synopsys/sim/verilog/altera	Contains the Verilog HDL functional simulation library for Verilog HDL projects.
./eda/synopsys/sim/vhdl/vital	Contains the VITAL 95 simulation library. You use this library when you perform functional simulation of the design before compiling it with the Quartus II software.
./eda/synopsys/mf	Contains behavioral VHDL models of some Altera macrofunctions, along with their component declarations. The a_81mux, a_8count, a_8fadd, and a_8mcomp macrofunctions are currently supported. Libraries in this directory allow you to instantiate, synthesize, and simulate these macrofunctions.
./eda/sim_lib	Contains the postrouting library for simulation.

3. The .synopsys_dc.setup configuration file allows you to set Synopsys Design Compiler variables. The compilers read .synopsys_dc.setup files from three directories, in the following order:

   1. The Synopsys root directory
   2. Your home directory
   3. The Design Compiler system directory

   The most recently read configuration file has highest priority. For example, a configuration file Design Compiler in the system directory has priority over the other configuration files, and a configuration file in the home directory has priority over a configuration file in the root directory.

   To set up your .synopsys_dc.setup configuration file:

1. Add the folllowing lines to your .synopsys_dc.setup configuration file. The following figure shows an excerpt from a sample file.

   Excerpt from Sample .synopsys_dc.setup File

   search_path = {./usr/quartus/synopsys/dc/syn/<device family>/lib};

   target_library = {<technology library>};

   symbol_library = {altera.sdb};

   link_library = {<technology library>};

   edifout_netlist_only = "true";

   edifout_power_and_ground_representation = "net";

   edifout_power_net_name = "VDD";

   edifout_ground_net_name = "GND";

   edifout_no_array = "false";

   edifin_power_net_name = "VDD";

   edifin_ground_net_name = "GND";

   compile_fix_multiple_port_nets = "true"

   bus_naming_style = "%s<%d>";

   bus_dimension_separator_style = "><";

   bus_inference_style = "%s<%d>";

   
   

2. Specify one of the Design Compiler technology libraries for the target_library and link_library parameters in the .synopsys_dc.setup file.

3. If you plan to instantiate architecture control logic functions from the alt_mf library, add the following line to your .synopsys_dc.setup file:

   define_design_lib altera -path /usr/quartus/eda/synopsys/mf/src 

   If you wish to use the VHDL System Simulator (VSS) software to simulate a VHDL design containing alt_mf library functions, you must compile this library with the /usr/quartus/eda/synopsys/bin/alt_mf.sh script.

4. Specify the device family for the <device family> variable in the search_path parameter.

4. Add the /usr/quartus/bin directory to the PATH environment variable in your .cshrc file in order to run the Quartus II software.

5. Source your .cshrc file by typing source .cshrc at the UNIX prompt.

6. To continue with the Design Compiler design flow with the DesignWare interface, proceed to 2. Set Up the DesignWare Interface. Otherwise, proceed to 3. Create a Design for Use with the Design Compiler Software.

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