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The DesignWare interface synthesizes designs by operator inference for all Altera^® devices supported by the Quartus^® II software except ARM^®-based Excalibur^™, MAX^® 3000, and MAX 7000 devices. It replaces the HDL operators +, -, >, <, >=, and <= with optimized design implementations.

Altera provides DesignWare synthetic libraries that are precompiled for the current version of Synopsys^® tools. These library files are located in the /usr/quartus/eda/synopsys/dc/syn/<device family>/lib directory.

To set up the DesignWare interface:

1. If you have not already done so, perform 1. Set up the Design Compiler Working Environment.

2. Add synthetic_library and define_design_lib parameters to your .synopsys_dc.setup configuration file and modify the link_library parameter as shown in Table 1 or Table 2.

   Table 1. DesignWare Parameters to Add to the .synopsys_dc.setup File for the Design Compiler Software
   Device Family	Parameters to Add to the .synopsys_dc.setup File
   ACEX® 1K	synthetic_library = {acex1k.sldb};  link_library = {acex1k.sldb acex1k.db};  define_design_lib DW_ACEX1K -path /usr/quartus/eda/synopsys/dw/lib
   APEX™ 20K	synthetic_library = {apex20k-3.sldb};  link_library = {apex20k-3.sldb apex20k-3.db};  define_design_lib DW_APEX20K-3 -path /usr/quartus/eda/synopsys/dw/lib
   APEX 20KC	synthetic_library = {apex20kc-3.sldb};  link_library = {apex20kc-3.sldb apex20kc-3.db};  define_design_lib DW_APEX20KC-3 -path /usr/quartus/eda/synopsys/dw/lib
   APEX 20KE	synthetic_library = {apex20ke-3.sldb};  link_library = {apex20ke-3.sldb apex20ke-3.db};  define_design_lib DW_APEX20KE-3 -path /usr/quartus/eda/synopsys/dw/lib
   APEX™ II	synthetic_library = {apexii-3.sldb};  link_library = {apexii-3.sldb apexii-3.db};  define_design_lib DW_APEXII-3 -path /usr/quartus/eda/synopsys/dw/lib
   Cyclone™	synthetic_library = {cyclone.sldb};  link_library = {cyclone.sldb cyclone.db};  define_design_lib DW_CYCLONE -path /usr/quartus/eda/synopsys/dw/lib
   FLEX® 6000	synthetic_library = {flex6000-(2|3).sldb};  link_library = {flex6000-(2|3).sldb flex6000-(2|3).db};  define_design_lib DW_FLEX6000-(2|3) -path /usr/quartus/eda/synopsys/dw/lib
   FLEX 10KE	synthetic_library = {flex10ke-3.sldb};  link_library = {flex10ke-3.sldb flex10ke-3.db};  define_design_lib DW_FLEX10KE-3 -path /usr/quartus/eda/synopsys/dw/lib
   Mercury™	synthetic_library = {mercury-3.sldb};  link_library = {mercury-3.sldb mercury-3.db};  define_design_lib DW_MERCURY-3 -path /usr/quartus/eda/synopsys/dw/lib
   Stratix™	synthetic_library = {stratix-3.sldb};  link_library = {stratix-3.sldb stratix-3.db};  define_design_lib DW_STRATIX-3 -path /usr/quartus/eda/synopsys/dw/lib
   Stratix™ GX	synthetic_library = {stratixgx.sldb};  link_library = {stratixgx.sldb stratixgx.db};  define_design_lib DW_STRATIXGX -path /usr/quartus/eda/synopsys/dw/lib

   
   

3. Specify the libraries listed in Table 2 as the synthetic library for the synthetic_library parameter and as the first of your link libraries for the link_library parameter in the .synopsys_dc_setup file.

   Table 2. DesignWare Synthetic Libraries
   Altera Device Family	Synopsys Design Compiler
   ACEX IK synthetic library	acex1k.sldb
   APEX 20K synthetic library	apex20k-3.sldb
   APEX 20KC synthetic library	apex20kc-3.sldb
   APEX 20KE synthetic library	apex20ke-3.sldb
   APEX II synthetic library	apexii-3.sldb
   Cyclone synthetic library	cyclone.sldb
   FLEX 6000 synthetic library	flex6000-2.sldb flex6000-3.sldb
   FLEX 10KE synthetic library	flex10ke-3.sldb
   Mercury synthetic library	mercury-3.sldb
   Stratix synthetic library	stratix-3.sldb
   Stratix GX synthetic library	stratixgx.sldb

4. If necessary, compile the DesignWare libraries. Altera provides precompiled DesignWare libraries, as described above. However, Altera also provides compilable source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare with any version of the Design Compiler. They also allow you to install components whose source is written in VHDL.

   To compile the DesignWare libraries for all Altera devices supported by the Quartus II software except ARM-based Excalibur and MAX 3000 devices, type the following commands at the UNIX prompt:

   cd /usr/quartus/eda/synopsys/bin 
dw_flex.sh 

5. To continue with the Design Compiler design flow, proceed to 3. Create a Design for Use with the Design Compiler Software.

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