Procedures

Commands

See Also

You can use the Synopsys^® Design Compiler design entry/synthesis tool to create, synthesize, and optimize a project and generate an EDIF Input File (.edf) for compilation in the Quartus^® II software. The following steps describe the typical flow to create, synthesize, and optimize a project, and create an EDIF Input File:

1. Set up the Design Compiler Working Environment

2. Set Up the DesignWare Interface

3. Create a Design for Use with the Design Compiler Software

4. Synthesize & Optimize a Design with the Design Compiler Software

More information is available on other EDA design entry/synthesis tools on the Altera® web site.

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