Altera/DesignWare Synthetic Libraries

The Altera^®/Synopsys^® DesignWare interface provides accurate area and timing prediction for designs that have been synthesized by the Synopsys design tools and targeted for ACEX^® 1K, APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, Cyclone^™, FLEX^® 6000, FLEX 10KE, Mercury^™, Stratix^™, and Stratix^™ GX devices. The DesignWare interface also ensures that the area and timing information closely matches the final device implementation generated by the Quartus^® II Compiler. The DesignWare interface synthesizes designs by operator inference. This interface supports bus widths of up to 32 bits, except adder functions, which support bus widths of up to 64 bits.

The Altera/DesignWare interface offers three major advantages to Synopsys designers:

Automatic access to carry and cascade chain functions
Optimal routing of designs
Improved area and performance prediction capability in Synopsys tools

Table 1 lists the Altera DesignWare synthetic libraries.

Altera Device Family	Synopsys Design Compiler
*Table 1. DesignWare Synthetic Libraries*
ACEX 1K synthetic library	acex1k.sldb
APEX 20K synthetic library	apex20k-3.sldb
APEX 20KC synthetic library	apex20kc-3.sldb
APEX 20KE synthetic library	apex20ke-3.sldb
APEX II synthetic library	apexii-3.sldb
Cyclone synthetic library	cyclone.sldb
FLEX 6000 synthetic library	flex6000-2.sldb flex6000-3.sldb
FLEX 10KE synthetic library	flex10ke-3.sldb
Mercury synthetic library	mercury-3.sldb
Stratix synthetic library	stratix-3.sldb
Stratix GX synthetic library	stratixgx.sldb

Table 2 lists functions included in the DesignWare synthetic libraries.

Name	Function
*Table 2. Synthetic Library Functions*
`flex_add`	Sum of A, B, and Carry-In
`flex_carry`	Carry of A, B, and Carry-In
`flex_sub`	Difference of A, B, and Borrow-In
`flex_borrow`	Borrow of A, B, and Borrow-In
`flex_gt,` `flex_sgt`	Greater than (`flex_gt` is unsigned; `flex_sgt` is signed)
`flex_carry_gt`	Greater than Carry
`flex_lt,` `flex_slt`	Less than (`flex_lt` is unsigned; `flex_slt` is signed)
`flex_carry_lt`	Less than Carry
`flex_gteq,` `flex_sgteq`	Greater than or equal to (`flex_gteq` is unsigned; `flex_sgteq` is signed)
`flex_carry_gteq`	Greater than or equal to Carry
`flex_inc`	Incrementer (Count = Count + 1)
`flex_carry_inc`	Incrementer Carry (Count = Count + 1)
`flex_dec`	Decrementer (Count = Count - 1)
`flex_carry_dec`	Decrementer Carry (Count = Count - 1)
`flex_lteq, flex_slteq`	Less than or equal to (`flex_lteq` is unsigned; `flex_slteq` is signed)
`flex_carry_lteq`	Less than or equal to Carry
`flex_count`	Counter
`aflex_carry_count`	Counter Carry
`flex_add_sub`	Adder/Subtractor
`flex_inc_dec`	Incrementer/Decrementer
`flex_umult, flex_smult`	Multiplier (`flex_umult` is unsigned; `flex_smult` is signed)

Refer to the Synopsys DesignWare Databook and VHDL Compiler Reference Manual for related information.

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