Altera VHDL & Verilog HDL alt_mf Logic Function Library (Design Compiler Software)

The alt_mf library contains behavioral VHDL and Verilog HDL models of the Altera^® logic functions shown in the following table. VHDL or Verilog HDL files that instantiate these functions can be simulated with the VHDL System Simulator (VSS) software or the Cadence Verilog-XL simulator, respectively, both before and after being compiled with the Synopsys^® Design Compiler software.

Name	Description
*Altera-Provided Architecture Control Logic Functions*
`a_8fadd`	8-bit full adder
`a_8mcomp`	8-bit magnitude comparator
`a_8count`	8-bit up/down counter
`a_81mux`	8-to-1 multiplexer

The behavioral descriptions of these four functions are contained in the /usr/quartus/eda/synopsys/mf/src directory, which contains the following files:

File:	Description:

mf.vhd	Contains behavioral VHDL descriptions of the logic functions.
mf_components.vhd	Contains VHDL Component Declarations for the logic functions.
mf.v	Contains behavioral Verilog HDL descriptions of the logic functions.

If you wish to simulate a VHDL design containing these logic functions, you can use the Altera-provided shell script /usr/quartus/eda/synopsys/bin/alt_mf.sh to create a design library called altera. This library allows you to reference the functions through the VHDL Library and Use Clauses, which direct the Design Compiler software to incorporate the library files when it compiles your top-level design file. The /usr/quartus/eda/synopsys/bin/alt_mf.sh shell script creates the altera design library by analyzing the VHDL System Simulator (VSS) simulation models in the /usr/quartus/eda/synopsys/mf/src directory.

Complete VHDL and Verilog HDL behavioral descriptions of these logic functions are included in the mf.vhd and mf.v files so that you can optionally retarget your design to other technology libraries.

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