See Also

You can instantiate Altera-provided logic functions from the alt_mf library, which includes the a_8fadd, a_8mcomp, a_8count, and a_81mux functions, in Verilog HDL designs. Altera^® provides behavioral Verilog HDL descriptions of these functions.

The following example shows an 8-bit counter that is instantiated using the a_8count function. Because Verilog HDL is case-sensitive, be sure to use uppercase letters for all of the macrofunction's module names and port names.

Sample Verilog HDL File with Logic Function Instantiation (counter.v)

module counter (clock, ena, load, dnup, set, clear, i, q, cout);
output          cout;
output[7:0]     q;
input[7:0]      i;
input           clock, ena, load, dnup, set, clear;
A_8COUNT u1    (.A(i[0]), .B(i[1]), .C(i[2]), .D(i[3]),
                .E(i[4]), .F(i[5]), .G(i[6]), .H(i[7]),
                .LDN(load), .GN(ena), .DNUP(dnup), .SETN(set), 
                .CLRN(clear), .CLK(clock), .QA(q[0]), .QB(q[1]),
                .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]),
                .QG(q[6]), .QH(q[7]), .COUT(cout) );
endmodule

The above sample can be synthesized with the Design Compiler software.

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