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The Quartus^® II/Synopsys^® interface offers full support for the memory capabilities for ACEX^® 1K, APEX^™ 20K, APEX^™ II, Cyclone^™, FLEX 10KE, Mercury^™, Stratix^™, and Stratix^™ GX devices, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. You can use the Altera^®-provided genmem utility to generate functional simulation models and timing models for these functions. Type genmem at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.

To instantiate a RAM or ROM function in Verilog HDL:

1. Use the genmem utility to generate a memory model by typing the following command at the UNIX prompt:

   genmem <memory type> <memory size> -verilog

   For example: genmem asynrom 256x15 -verilog

2. Create a Verilog HDL design that instantiates the <memory name> function.

   The following example shows a Verilog HDL design that instantiates asyn_rom_256x15.v, a 256 x 15 ROM function.

   Figure 1: Verilog HDL File with ROM Instantiation (tstrom.v)

   module tstrom (addr, enab, q); parameter LPM_FILE = "u1.hex"; input [7:0] addr; input enab; output [14:0] q;

   asyn_rom_256x15 // synopsys translate_off #(LPM_FILE)

   // synopsys translate_on u1 (.Address(addr), .Q(q), .MemEnab(enab)); endmodule

3. (Optional for RAM functions) Specify an initial memory content file:

   • For ROM functions, you must specify the file name of an initial memory content file in the Hexadecimal (Intel-Format) File (.hex) or the Altera Memory Initialization File (.mif) format in the Parameter Statement, with the LPM_FILE parameter. See Figure 1. The file name must be the same as the instance name; for example, the u1 instance name must be unique throughout the whole project. The initialization file must reside in the directory containing the project's design files.

   • For RAM functions, specifying a MIF is optional. If you want to use it, you must specify it in a Parameter Statement, as described above.

   The MIF format is supported only for specifying initial memory content when compiling designs within Quartus II software. You cannot use a MIF to perform simulation with Synopsys tools prior to compilation with the Quartus II software. If you use an HEX File and wish to simulate the design with the VHDL System Simulator (VSS) after compilation with the Quartus II software, you should use the Synopsys intelhex utility to translate the HEX File into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.

4. In the Verilog HDL design, add // synopsys translate_off before the Parameter Statement, and add // synopsys translate_on after the Parameter Statement. These directives tell the HDL Compiler for Verilog when to stop and start synthesizing. See Figure 1.

5. The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information that the Synopsys Design Compiler software can use. You must add this timing model to the existing library so that the compiler can access the timing information. Type the following commands at the dc_shell prompt:

   read -f db apex20k[<speed grade>].db update_lib apex20k[<speed grade>] <RAM/ROM function name>.lib

6. (Optional) Include the following command to update your apex20k[<speed grade>].db file with the RAM/ROM timing information:

   write_lib apex20k[<speed grade>] -o apex20k[<speed grade>].db

7. When you generate the EDIF netlist file from the design, include the bus structure from the RAM or ROM function(s).

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