DesignWare Up/Down Counter Function Instantiation Example for VHDL

The Altera^® DesignWare Libraries for all Altera devices supported by the Quartus^® II software except for MAX^® 3000 and MAX 7000 devices allow you to instantiate the DW03_updn_ctr function, which is the same as the Synopsys^® DW03 up/down counter. This function allows you to use the same VHDL code regardless of which device is targeted.

The following example shows a VHDL file excerpt with DW03_updn_ctr instantiation.

VHDL File Excerpt with Up/Down Counter Instantiation

LIBRARY ieee,DW03;
USE ieee.std_logic_1164.all;
USE DW03.DW03_components.all;

ENTITY updn_4 IS
   PORT (D : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
      UP_DN, LD, CE, CLK, RST: IN STD_LOGIC;
      TERCNT : OUT STD_LOGIC;
      Q      : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0));
END updn_4;

ARCHITECTURE structure OF updn_4 IS

BEGIN
   u0: DW03_updn_ctr
   GENERIC MAP(width => 4)
   PORT MAP (data => d, clk => clk, reset => rst, up_dn => up_dn,
             load => ld, tercnt => tercnt, cen => ce, count => q);
END structure;

- PLDWorld -

Created by chm2web html help conversion utility.