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To perform a timing simulation of a Quartus^® II–generated VHDL Output File (.vho) and the corresponding Standard Delay Format Output File (.sdo) with the Cadence NC-VHDL software:

To simulate VHDL Output Files with the NC-VHDL software:

1. If you have not already done so, perform 1. Set Up the NC-VHDL Working Environment.

2. To generate the VHDL Output File (.vho):

   1. Specify EDA tool settings in the Quartus II software.

   2. Compile the design with the Quartus II software.

   The Quartus II Compiler generates the VHDL Output File and the SDF Output File and places them in the /<project directory>/simulation/ncsim directory. More Details

3. Copy the cds.lib and hdl.var files, which are located in the \<NC-VHDL installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

4. To map the <device family> variable to a device-specific directory and to map the work library to the physical location of the work library, add the following lines to the cds.lib file:

   DEFINE <device family> ./<device family>
   DEFINE <work library> ./work

5. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix^™ GX timing simulation model libraries:

DEFINE stratixgx_gxb \quartus\eda\sim_lib\ncsim\vhdl\stratixgx_gxb

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

6. Create a work library in the project directory by typing the following command at a command prompt: More Details

mkdir <work library> 

7. Start the NC-VHDL software by typing the following command at the command prompt:

   ncdesktop  (For PCs)
   nclaunch  (For UNIX workstations)

8. To create a work library, select Add > New Library (Edit menu) and type the name of the work library in the Library box. More Details

When you run the NC-VHDL software automatically after compilation in the Quartus II software, the NC-VHDL software automatically performs steps 4 through 7.

9. To compile the appropriate project files and libraries into the work library:

   1. Choose VHDL Compiler (Tools menu).

   2. In the File box, type the path of the test bench file (if you are using one).

   3. In the Work Library list, select the work library.

   4. Click OK.

   5. Repeat steps 8a to 8d to compile the VHDL Design File (.vhd) for the project and the appropriate Altera^® postrouting library.

      For VHDL 93-compliant designs, turn on Enable VHDL 93 features in the VHDL Compiler dialog box.

10. To compile the SDF Output File:

    1. Choose SDF Compiler (Tools menu).

    2. In the SDF File box, specify the name of the SDF Output File for the project.

    3. Make sure <project name>.sdf.X appears in the Output file name box.

    4. Click OK.

11. To elaborate the design, choose Elaborator (Tools menu) and type <work library>.<top-level entity name> in the Design Unit box.

12. To simulate the design, choose Simulator (Tools menu) and type <work library>.<top-level entity name> in the Snapshot box.

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