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To use the Cadence NC-VHDL software to perform a functional simulation of a VHDL design that contains Altera-specific components:

1. If you have not already done so, perform 1. Set Up the NC-VHDL Working Environment.

2. Start the NC-VHDL software by typing the following command at the command prompt:

   ncdesktop  (For PCs)
   nclaunch  (For UNIX workstations)

3. To create a work directory, select Add > New Library (Edit menu) and type the name of the work library in the Library box. More Details

4. Copy the cds.lib and hdl.var files, which are located in the \<NC-VHDL installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

5. Edit the cds.lib and hdl.var files as follows:

   File Name	File Contents	Function
   cds.lib	DEFINE <work library> ./work DEFINE LPM <work library> DEFINE ALTERA_MF <work library>	Maps the <work library> to the physical location of the work library, and the variables LPM and ALTERA_MF to the work library.
   hdl.var	DEFINE WORK <work library>	Maps the NC-VHDL variable WORK to the <work library>.

6. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix^™ GX functional simulation model libraries:

DEFINE altgxb \quartus\eda\sim_lib\ncsim\vhdl\altgxb

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

7. To compile the appropriate project files and libraries into the work library:

   1. Choose VHDL Compiler (Tools menu).

   2. Type in the path of the test bench file (if you are using one) in the File box.

   3. In the Work Library list, select the work library.

   4. Click OK.

   5. Repeat steps 7a through 7d to compile the VHDL Design File (.vhd) for the project and the appropriate functional simulation library.

   For VHDL 93-compliant designs, turn on Enable VHDL 93 features in the VHDL Compiler dialog box.

8. To elaborate the design, select Elaborator (Tools menu) and type <work library>.<top-level entity name> in the Design Unit box.

9. To simulate the design, choose Simulator (Tools menu) and type <work library>.<top-level entity name> in the Snapshot box.

10. To continue with the NC-VHDL simulation flow, proceed to one of the following steps:

    • 3. Perform a Timing Simulation with the NC-VHDL Software
    • 3. Perform a Timing Simulation with the NC-VHDL Software (Command-Line)

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