eda

3. Perform a Timing Simulation with the NC-VHDL Software (Command-Line)

To perform a timing simulation of a Quartus® II–generated VHDL Output File (.vho) and Standard Delay Format Output Files (.sdo) using command line commands with the Cadence NC-VHDL software:

  1. If you have not already done so, perform 1. Set Up the NC-VHDL Working Environment.

  2. To generate the VHDL Output File (.vho):

    1. Specify EDA tool settings in the Quartus II software.

    2. Compile the design with the Quartus II software.

    NOTE The Quartus II Compiler generates the VHDL Output File and the SDF Output File and places them in the /<project directory>/simulation/ncsim directory. More Details

  3. Create a work library in the project directory by typing the following command at the command prompt: More Details

    4. mkdir <work library> Enter

  4. Copy the cds.lib and hdl.var files, which are located in the \<NC-VHDL installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

  5. To map the <device family> variable to a device-specific directory and to map the work library to the physical location of the work library, add the following lines to the cds.lib file:

    DEFINE <device family> ./<device family>
    DEFINE <work library> ./work

  6. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix™ GX timing simulation model libraries:

    7. DEFINE stratixgx_gxb \quartus\eda\sim_lib\ncsim\vhdl\stratixgx_gxb

    NOTE If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

    NOTE When you run the NC-VHDL software automatically after compilation in the Quartus II software, the NC-VHDL software automatically performs steps 4 and 5.

  7. To annotate the timing data in the SDF Output File:

    1. Compile the SDF Output File using the ncsdfc utility by typing the following command at the command prompt:

      ncsdfc <project name>_vhd.sdo  Enter

      The ncsdfc utility generates a <project name>.sdf.X compiled SDF Output File and places it in the /<project directory>/simulation/ncsim directory.

    2. Specify the compiled SDF Output File for the project by adding the following line to the SDF command file for the project:

      COMPILED_SDF_FILE = "<project name>.sdf.X

  8. To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:

    9. ncvhdl <test bench file> Enter
    ncvhdl <project name>.vho Enter
    ncvhdl -v93 -work <device family> \quartus\eda\sim_lib\<device family>_atoms.vhd Enter
    ncvhdl -v93 -work <device family> \quartus\eda\sim_lib\<device family>_components.vhd Enter

    NOTE

    For VHDL 87-compliant designs for APEX™ 20KE devices, type the following command to compile the simulation model library instead:

    ncvhdl [-v87] -work <device family> \quartus\eda\sim_lib\apex20ke_atoms_87.vhd Enter

  9. To elaborate and simulate the design, type the following commands at the command prompt:

    10. ncelab -sdf_cmd_file <SDF command file name> <work library>.<top-level entity name> Enter
    ncsim <work library>.<top-level entity name> Enter


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