Overviews

Commands

See Also

To perform a timing simulation of a Quartus^® II–generated Verilog Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Cadence Verilog-XL software:

1. If you have not already done so, perform 1. Set Up the Verilog-XL Working Environment.

2. To generate the Verilog Output File (.vo):

   1. Specify EDA tool settings in the Quartus II software.

   2. Compile the design with the Quartus II software.

   The Quartus II Compiler generates the Verilog Output File and the SDF Output File and places them in the /<project directory>/simulation/verilogXL directory. More Details

3. Using any standard text editor, create a test bench file that includes test vectors for the design.

4. To start the Verilog-XL software and simulate the Verilog Output Files and SDF Output Files, type the following command at the command prompt:

   verilog <test bench>.v <design name>.vo /quartus/eda/sim_lib/<device family>_atoms.v 

   If your design contains the altgxb megafunction, you must also specify the stratixgx_hssi_atoms.v timing simulation library, located in the \quartus\eda\sim_lib\verilog_xl\ directory. You must also set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

Back to Top