Options for Individual Nodes Only Section (Settings and Configuration Files)

The Options for Individual Nodes Only section lists specified options for individual nodes for the compilation focus entity. The Options for Individual Nodes Only section is located in the Entity Settings File (.esf).

The Options for Individual Nodes Only section keyword OPTIONS_FOR_INDIVIDUAL_NODES_ONLY.

The Options for Individual Nodes Only section contains statements that follow these Usage Code definitions.

The following table shows the Options for Individual Nodes Only section keywords (which are underscore separated), descriptions, legal settings, and usage codes:

Keyword	Settings	Code
`APEX^™20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS`	On \| Off \| Small \| Medium \| Large	B
`APEX20K_LOCAL_ROUTING_SOURCE`	On \| Off	B
`CLOCK_ENABLE_ROUTING`	Peripheral \| Single Pin	B
`CLKLOCKX1_INPUT_FREQ`	On \| Off	B
`CURRENT_STRENGTH`	Default Strength \| Min Strength \| Max Strength \| Strength 2mA \| Strength 4mA \| Strength 8mA \| Strength 12mA \| Strength 16mA \| Strength 24mA	B
`DECREASE_INPUT_DELAY_TO_INPUT_REGISTER`	On \| Off	B
`DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER`	On \| Off	B
`DELAY_SETTING_FROM_VIO_TO_CORE`	<time>	B
`DQS_FREQUENCY`	<time>	B
`DQS_SHIFT`	Phase of 0 degrees \|Phase of 90 degrees \| Phase of 72 degrees	B
`DQS_SYSTEM_CLOCK`	<string>	B
`DUPLICATE_ATOM`	<string>	C
`FAST_INPUT_REGISTER`	On \| Off	B
`FAST_OUTPUT_ENABLE_REGISTER`	On \| Off	B
`FAST_OUTPUT_REGISTER`	On \| Off	B
`FASTROW_INTERCONNECT`	On \| Off	B
`FLEX^®6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS`	On \| Off	B
`FLEX6K_LOCAL_ROUTING_SOURCE`	On \| Off	B
`FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS`	On \| Off	B
`GLOBAL_SIGNAL`	On \| Off \| Global Clock \| Regional Clock \| Fast Regional Clock	B
`IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL`	On \| Off	B
`INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN`	On \| Off	B
`INCREASE_DELAY_TO_OUTPUT_PIN`	On \| Off	B
`INCREASE_INPUT_CLOCK_ENABLE_DELAY`	On \| Off \| Small \| Large	B
`INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER`	On \| Off \| Small \| Large	B
`INCREASE_OUTPUT_CLOCK_ENABLE_DELAY`	On \| Off \| Small \| Large	B
`INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY`	On \| Off \| Small \| Large	B
`INCREASE_TZX_DELAY_TO_OUTPUT_PIN`	On \| Off	B
`INPUT_REFERENCE`	As VREFA \| As VREFB \| Off	B
`INSERT_ADDITIONAL_LOGIC_CELL`	On \| Off	B
`LCELL_INSERTION`	<integer>	B,C
`LVDS_FIXED_CLOCK_DATA_PHASE`	Default \| Negative 180 \| Negative 90 \| Zero \| Positive 90 \| Positive 180	B
`MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS`	On \| Off \| Small \| Medium \| Large	B
`OUTPUT_ENABLE_REGISTER_DUPLICATION`	On \| Off	B
`OUTPUT_ENABLE_ROUTING`	Peripheral \| Single Pin	B
`PLL_COMPENSATE`	On \| Off	B
`ROW_GLOBAL_SIGNAL`	On \| Off	B
`STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS`	On \| Off \| Small \| Medium \| Large	B, C
`STRATIXGX_TERMINATION_VALUE`	Off \| OCT 100 Ohms \| OCT 120 Ohms \| OCT 150 Ohms	B
`TERMINATION`	Off \| Series \| Parallel \| Differential	B
`USE_CLK_FOR_VIRTUAL_PIN`	<clock name>	B
`VIRTUAL_PIN`	On \| Off	B

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