A logic option that uses FastRow^™ interconnect to route the fan-outs of an input or bidirectional pin. Both the pin and its fan-out(s) must also be assigned to the same Fast Region. The FastRow Interconnect option is ignored if it is applied to anything other than a column (vertical) pin that is implemented as an input or bidirectional pin.

This option is also ignored if it is applied to anything other than an input or bidirectional pin. This option is available for APEX^™ 20KC, APEX 20KE, APEX^™ II, and ARM^®-based Excalibur^™ devices.