A logic option that determines the propagation delay from the interior of the device to the clock enable input of an output enable register. This is an advanced option that should be used only after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory.
You can select one of the following settings:
| Small | Implements a small increase to the output delay. Creates more propagation delay from the interior of the device to the clock enable input of the output enable register than is allowed by the Large setting. |
| Large | Implements a large increase to the output delay. Creates less propagation delay from the interior of the device to the clock enable input of the output enable register than is allowed by the Compiler's internal default setting. |
| On | Creates the maximum propagation delay from the interior of the device to the clock enable input of the output enable register. |
| Off | Creates no extra output delay and yields the least propagation delay from the interior of the device to the clock enable input of the output enable register. This is the default setting. |
This option is ignored if it is applied to anything other than an I/O cell that has an output enable register with a clock enable signal. For detailed information on how to use this option, refer to the data sheet for the device family, which is available from the Literature section of the Altera® web site. This option is available for Stratix™ and Stratix™ GX devices.
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