A logic option that specifies the name of the clock to be used for the I/O element specified with the Virtual Pin logic option. The clock used for the virtual pin can be a pin or an internal node. If you turn on the Virtual Pin logic option but do not specify a clock with the Virtual Pin Clock logic option or the clock you specified does not exist, the Compiler finds a clock by traversing the fan-in and fan-out of the I/O element. If there are no clocks in the fan-in and fan-out of the I/O element, the Compiler assigns the clock to GND.

This option is ignored if it is applied to anything other than an input pin or an output pin. This option is available for APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, ARM^®-based Excalibur^™, Cyclone^™, Mercury^™, Stratix^™, and Stratix^™ GX devices.

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