A logic option that increases the propagation delay to the output enable pin from internal logic or the output enable register implemented in an I/O cell. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family. This option is off by default.

This option is ignored if it is applied to anything other than an output enable pin. This option is available for APEX^™ II, Mercury^™, Stratix^™, and Stratix^™ GX devices.